Abstract
This work proposes and tests an algorithm for batching and dispatching lots along cleaning and diffusion operations of a wafer fab. These are characterised by: 1) time constraints (i.e., the time between the end of an operation 'n' and the start of the operation 'n + q' must be lower than a time limit, in order to guarantee the lots' quality); 2) absence of batching affinity between operations. Literature so far has been falling short in proposing scheduling algorithms suitable for this context. Therefore, we propose two heuristic algorithms to minimise the average flow time and the number of re-cleaned lots, maximise machine saturation and avoid scrapped lots. Discrete-event simulation was used to test the performance of the two algorithms using real data of STMicroelectronics. The formerly proposed model outperforms the latter. Therefore, STMicroelectronics implemented the former in its fab in Catania gaining an increase in the average Overall equipment effectiveness of 7%.
